Interconnected high speed electron tunneling devices

ABSTRACT

An integrated circuit chip includes a formation of integrated layers configured to define at least one integrated electronic component. The integrated layers further define an integrated electron tunneling device, which includes first and second non-insulating layers spaced apart from one another such that a given voltage can be provided thereacross. The integrated electron tunneling device further includes an arrangement disposed between the first and second non-insulating layers and serving as a transport of electrons between and to the first and second non-insulating layers. The arrangement includes at least a first layer configured such that the transport of electrons includes, at least in part, transport by means of tunneling. The integrated electron tunneling device further includes an antenna structure connected with the first and second non-insulating layers, and the integrated electron tunneling device is electrically connected with the integrated electronic component.

RELATED APPLICATION

The present application is a Continuation of copending application Ser.No. 10/337,427 filed Jan. 6, 2003; which is a Continuation-in-Part ofthe four following applications: 1) application Ser. No. 09/860,988filed on May 21, 2001 and issued as U.S. Pat. No. 6,534,784 on Mar. 18,2003; 2) application Ser. No. 09/860,972 filed on May 21, 2001 andissued as U.S. Pat. No. 6,563,185 on May 13, 2003; 3) application Ser.No. 10/103,054 filed on Mar. 20, 2002 and issued as U.S. Pat. No.7,010,183 on Mar. 7, 2006; and 4) application Ser. No. 10/140,535 filedMay 6, 2002; all of which applications are incorporated herein byreference in their entirety.

BACKGROUND OF THE INVENTION

The present invention relates generally to optoelectronic devices and,more particularly, to interconnection of optoelectronic devicesincluding electron tunneling devices.

Increased amounts and speed of data transfer in communication andcomputing systems pose a challenge to the current state of devicetechnology. Large quantities of information must be transferred quicklyacross distances ranging from very short distances, from between chipsas well as between boards containing chips, to longer distances betweenracks of devices, very short reach (VSR)/optical Ethernet and beyond.Even with the development of high-speed communications switches androuters, the data must be taken in and out of such high-speed devices atcompatibly high rates in order for the entire system to functionefficiently.

Radio frequency (RF) inter-chip and intra-chip connections have beendeveloped as a possible way of transferring data within and betweenchips. However, RF interconnects use large antennae and/or waveguides onor connected to chips, thus requiring valuable on-chip and device “realestate.” Also, RF interconnects are limited in data transfer speed dueto the use of radio frequencies.

Other researchers have suggested the use of optical signals as analternative to electrical signals in providing inter- and intra-chipconnections.¹ For instance, parallel fiber-optic interconnects which areedge-connected to semiconductor devices have been developed for usewithin systems with a large number of electronic components (e.g.,computers).² Although optical interconnect technology promises thepossibility of higher rate data transfer than electrical interconnects,optical interconnect technology, as heretofore suggested, is still costprohibitive in comparison. There is potentially a huge market for highspeed interconnect arrangements because all desktop computers and localarea networks would benefit from the use of high speed interconnectsbetween components on chips, between chips, etc.

As will be seen hereinafter, the present invention provides asignificant improvement over the prior art as discussed above by virtueof its ability to provide the increased performance while, at the sametime, having significant advantages in its manufacturability. Thisassertion is true for electromagnetic devices generally, which takeadvantage of the present invention, as well as data communication andcomputing devices in particular.

BRIEF SUMMARY OF THE INVENTION

As will be described in more detail hereinafter, there is disclosedherein an integrated circuit chip including a formation of integratedlayers. The integrated layers are configured so as to define at leastone integrated electronic component as well as an integrated electrontunneling device. The integrated electron tunneling device includesfirst and second non-insulating layers spaced apart from one anothersuch that a given voltage can be provided across the first and secondnon-insulating layers. The integrated electron tunneling device furtherincludes an arrangement disposed between the first and secondnon-insulating layers and configured to serve as a transport ofelectrons between and to the first and second non-insulating layers. Thearrangement includes at least a first layer configured such that thetransport of electrons includes, at least in part, transport by means oftunneling. The integrated electron tunneling device further includes anantenna structure connected with the first and second non-insulatinglayers, and the integrated electron tunneling device is electricallyconnected with the integrated electronic component.

In one aspect of the invention, a method for fabricating an integratedcircuit chip is disclosed. The method includes forming a plurality ofintegrated layers, where the forming step includes the steps of definingat least one integrated electronic component and defining an integratedelectron tunneling device. The integrated electron tunneling deviceincludes first and second non-insulating layers spaced apart from oneanother such that a given voltage can be provided across the first andsecond non-insulating layers. The integrated electron tunneling devicefurther includes an arrangement disposed between the first and secondnon-insulating layers and configured to serve as a transport ofelectrons between and to the first and second non-insulating layers. Thearrangement includes at least a first layer configured such that thetransport of electrons includes, at least in part, transport by means oftunneling. The integrated electron tunneling device further includes anantenna structure connected with the first and second non-insulatinglayers. The method further includes electrically connecting theintegrated electron tunneling device with the integrated electroniccomponent.

In another aspect of the invention, an integrated circuit chip includesa formation of integrated layers, which integrated layers are configuredso as to define at least one integrated electronic component. Theintegrated circuit chip also includes an electron tunneling deviceincluding first and second non-insulating layers spaced apart from oneanother such that a given voltage can be provided across the first andsecond non-insulating layers. The electron tunneling device furtherincludes an arrangement disposed between the first and secondnon-insulating layers and configured to serve as a transport ofelectrons between and to the first and second non-insulating layers. Thearrangement includes at least a first layer configured such that thetransport of electrons includes, at least in part, transport by means oftunneling. The electron tunneling device further includes an antennastructure connected with the first and second non-insulating layers, andthe electron tunneling device is formed on top of and separately fromthe formation of integrated layers without interference with an intendedfunction of the integrated electronic component and its spatial locationwhile being electrically connected with the integrated electroniccomponent.

In still another aspect of the invention, an integrated circuit chipincludes a formation of integrated layers, which formation of integratedlayers is configured to define at least one integrated electroniccomponent and is further configured to define an integratedoptoelectronic device having an antenna. The antenna is configured toreceive an optical signal. The integrated optoelectronic device iselectrically connected with the integrated electronic component.

In yet another aspect of the invention, an integrated circuit chipincludes a formation of integrated layers defining at least oneintegrated electronic component. The integrated circuit chip alsoincludes an optoelectronic device having an antenna, which antenna isconfigured to receive an optical signal incident thereon. Theoptoelectronic device is formed on top of and separately from theformation of integrated layers without interference with an intendedfunction of the integrated electronic component and its spatial locationwhile being electrically connected with the integrated electroniccomponent. In an alternative embodiment, the optoelectronic device isconfigured to provide an optical signal while the antenna is configuredinstead to transmit the optical signal.

In a further aspect of the invention, an integrated circuit chipincludes at least one substrate and circuitry formed on the substrate,which circuitry includes at least first and second integrated electroniccomponents. The integrated circuit chip also includes a firstoptoelectronic device for providing an optical signal. The firstoptoelectronic device includes a first antenna, which first antenna isconfigured to emit the optical signal, and the first optoelectronicdevice is supported on the substrate while being electrically connectedwith the first integrated electronic component. The integrated circuitchip further includes a second optoelectronic device. The secondoptoelectronic device includes a second antenna, which second antenna isconfigured to receive the optical signal from the first antenna suchthat first and second optoelectronic devices are in opticalcommunication with one another, while the second optoelectronic deviceis also supported on the substrate and is electrically connected withthe second integrated electronic component.

In a still further aspect of the invention, an integrated circuitassembly includes first and second substrates. First circuitry,including at least a first integrated electronic component, is formed onthe first substrate, and second circuitry, including at least a secondintegrated electronic component, is formed on the second substrate. Theintegrated circuit assembly also includes a first optoelectronic devicefor providing an optical signal. The first optoelectronic deviceincludes a first antenna, which is configured to emit the opticalsignal, and is supported on the first substrate while being electricallyconnected with the first integrated electronic component. The integratedcircuit assembly further includes a second optoelectronic deviceincluding a second antenna. The second optoelectronic device issupported on the second substrate and is electrically connected with thesecond integrated electronic component. The second antenna is configuredto receive the optical signal from the first antenna such that the firstand second optoelectronic devices are in optical communication with oneanother.

In another aspect of the invention, an assembly includes anoptoelectronic system, in which an optical signal is present and whichincludes at least one optoelectronic device configured to act on theoptical signal. The assembly also includes an electron tunneling devicealso configured to act on the optical signal. The electron tunnelingdevice includes first and second non-insulating layers, which are spacedapart from one another such that a given voltage can be provided acrossthe first and second non-insulating layers, and an arrangement disposedbetween the first and second non-insulating layers, which arrangement isconfigured serve as a transport of electrons between and to the firstand second non-insulating layers. The arrangement includes a firstamorphous layer configured such that using only the first amorphouslayer in the arrangement would result in a given value of nonlinearityin the transport of electrons, with respect to the given voltage. Thearrangement also includes a different, second layer disposed directlyadjacent to and configured to cooperate with the first amorphous layersuch that the transport of electrons includes, at least in part,transport by means of tunneling through the first amorphous layer andthe second layer, and such that the nonlinearity, with respect to thegiven voltage, is increased over and above the given value ofnonlinearity by the inclusion of the second layer without the necessityfor any additional layer. The assembly further includes an opticalconfiguration cooperating with the electron tunneling device and withthe optoelectronic device such that the optical signal is transmittedtherebetween.

In a still another aspect of the invention, a device includes awaveguide, which waveguide in turn includes an optical input port. Theoptical input port is configured for receiving an input light. Thewaveguide also includes an optical output port and is configured fordirecting the input light from the optical input port toward the opticaloutput port. The device also includes an optoelectronic assembly, whichincludes an electron tunneling device. The electron tunneling deviceincludes first and second non-insulating layers, which are spaced apartfrom one another such that a given voltage can be provided thereacross,and an arrangement disposed between the first and second non-insulatinglayers and configured to serve as a transport of electrons between andto the first and second non-insulating layers. The arrangement includesat least a first layer configured such that the transport of electronsincludes, at least in part, transport by means of tunneling. Theoptoelectronic assembly also includes a coupling arrangement configuredto cooperate with the electron tunneling device and the waveguide forcoupling at least a portion of the input light from the waveguide intothe electron tunneling device.

In yet another aspect of the invention, an arrangement includes anoptical waveguide with an optical input port, which optical input portis configured for receiving an input light, and an optical output port.The optical waveguide is configured for directing the input light fromthe optical input port toward the optical output port. The arrangementfurther includes an optoelectronic assembly with a surface plasmondevice, which is configured to act on an input signal. The surfaceplasmon device includes a device input port, which is configured toreceive the input signal, a device output port and a structure includinga tunneling junction connected with the device input port and the deviceoutput port. The tunneling junction is configured in a way (i) whichprovides electrons in a particular energy state within the structure,(ii) which produces surface plasmons in response to the input signal,(iii) which causes the structure to act as a surface plasmon waveguidefor directing at least a portion of the surface plasmons along apredetermined path toward the device output port such that the surfaceplasmons so directed interact with the electrons in a particular way,and (iv) which produces at the device output port an output signalresulting from the particular interaction between the electrons and thesurface plasmons. The optoelectronic assembly further includes acoupling arrangement, which is configured to cooperate with the surfaceplasmon device and the optical waveguide for coupling at least a portionof the input light from the waveguide into the surface plasmon device asthe input signal.

In a further aspect of the invention, an integrated circuit chipincludes a substrate and a formation of integrated layers supported onthe substrate, which integrated layers are configured so as to define atleast one integrated electronic component. The integrated circuit chipalso includes an optical waveguide, which is also supported on thesubstrate and includes an optical input port configured for receiving aninput light including a clock signal encoded thereon. The integratedcircuit chip further includes at least one optoelectronic assemblyelectrically connected with the integrated electronic component andincluding an electron tunneling device. The electron tunneling deviceincludes first and second non-insulating layers spaced apart from oneanother such that a given voltage can be provided thereacross. Theelectron tunneling device also includes an arrangement disposed betweenthe first and second non-insulating layers and configured to serve as atransport of electrons between and to the first and second non-insultinglayers. The arrangement includes at least a first layer configured suchthat the transport of electrons includes, at least in part, transport bymeans of tunneling. The optoelectronic assembly also includes a couplingarrangement configured to cooperate with the electron tunneling deviceand the optical waveguide for coupling at least a portion of the inputlight including the clock signal from the waveguide into the electrontunneling device. The electron tunneling device is configured to (i)receive the portion of the input light, (ii) produce an electric signaland (iii) transmit the electric signal toward the integrated electroniccomponent electrically connected with the optoelectronic assembly foruse by the integrated electronic component.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

The present invention may be understood by reference to the followingdetailed description taken in conjunction with the drawings brieflydescribed below. It is noted that, for purposes of illustrative clarity,certain elements in the drawings may not be drawn to scale.

FIG. 1A is a diagrammatic illustration, in perspective view, of aninterconnected electron tunneling device of the present invention, shownhere to illustrate an embodiment including a planar waveguide on a chipas the interconnection.

FIGS. 1B and 1C are diagrammatic illustrations, in cross-section,showing details of electron tunneling devices suitable for use in theinterconnected electron tunneling device of the present invention.

FIG. 1D is a diagrammatic illustration, in perspective view, of analternative embodiment of an interconnected electron tunneling device ofthe present invention, shown here to illustrate the use of a doubleantenna electron tunneling device.

FIGS. 1E and 1F are diagrammatic illustrations, in perspective view, ofadditional embodiments of an interconnected electron tunneling device ofthe present invention, shown here to illustrate the use of surfaceplasmon devices.

FIGS. 2A and 2B are diagrammatic illustrations, in cross-section, ofembodiments of an edge-fed, optical clock distribution scheme of thepresent invention.

FIGS. 3A and 3B are diagrammatic illustrations of a top-fed, opticalclock distribution scheme of the present invention.

FIGS. 4A-4D are diagrammatic illustrations of another interconnectedelectron tunneling device of the present invention, shown here toillustrate embodiments including optical fiber as the interconnectionbetween devices on separate chips.

FIG. 5 is a diagrammatic illustration of still another interconnectedelectron tunneling device in accordance with the present invention,shown here to illustrate the use of free-space optical interconnectionbetween electron tunneling devices on separate chips.

FIGS. 6A-6E are diagrammatic illustrations of a waveguide-coupled deviceof the present invention, shown here to illustrate various embodimentsof the coupling of electron tunneling devices with a waveguide, as usedin the aforementioned interconnected electron tunneling devices.

FIGS. 7A-7D are diagrammatic illustrations of an alternativewaveguide-coupled device of the present invention and applications.

FIGS. 8A-8C are diagrammatic illustrations, in perspective view, ofexamples of packaging options and applications for the waveguide-coupleddevice of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The following description is presented to enable one of ordinary skillin the art to make and use the invention and is provided in the contextof a patent application and its requirements. Various modifications tothe described embodiments will be readily apparent to those skilled inthe art and the generic principles herein may be applied to otherembodiments. Thus, the present invention is not intended to be limitedto the embodiment shown but is to be accorded the wildest scopeconsistent with the principles and features described herein.

As described in the Background section, there is a growing need for highspeed interconnection between devices over short distances, such asbetween racks, boards, chips, as well as between components located on asingle chip. These interconnection arrangements must be capable of highspeed transmission of data and should be low cost. The interconnectionarrangements and systems need to be competitive and compatible withcurrent state-of-the-art electrical interconnects in terms of cost,speed, power, distance, requirement for signal processing and allowanceof plug-n-play. For low cost, high speed and highest level ofintegration, the interconnect components may be integrated directly ontosilicon integrated circuitry. The interconnect should ideally becompatible with standardized systems and interfaces provided by existingsuppliers. In order to accommodate the current state of the technology,the interconnect should be compatible with multi-mode fibers and be timedivision multiplexing (TDM) or coarse wavelength division multiplexing(CWDM) compatible. Alternatively, depending on the application in whichthe interconnect is to be used, single-mode fibers might also be used.Polarization-insensitivity is desirable in order to reduce signal loss.VCSEL devices are the mainstay light sources in the current art;therefore the interconnection arrangement should be compatible withVCSEL devices. Currently-available VCSEL devices operate at 850 nm and,potentially, at 1300 and 1550 nm wavelengths. Furthermore, currentVCSELs operate at 2.5 Gbps, while 10 Gbps and, in the future, 80 Gbpsdevices may be available. The interconnect should also betemperature-insensitive in order for the interconnect to be incorporatedonto silicon integrated circuitry. For example, as will be described indetail hereinafter, the interconnect may be top-side coupled ontoCMOS-integrated components.

Recent progress in tunneling junction technology by the assignee of thepresent application has greatly increased the flexibility in fabricationand design of electron tunneling devices based onmetal-insulator(s)-metal structures, thus allowing the fabrication ofhigh speed electron tunneling devices (See, copending U.S. patentapplication Ser. No. 09/860,988 Attorney Docket Number Phiar-P001(hereinafter, '988 application), Ser. No. 09/860,972 Attorney DocketNumber Phiar-P002 (hereinafter, '972 application), Ser. No. 10/103,054Attorney Docket Number Phiar-3 (hereinafter, '054 application), Ser. No.10,140,545 Attorney Docket Number Phiar-3cip (hereinafter '535application) and Ser. No. 10/265,935 Attorney Docket Number Phiar-1cip(hereinafter '935 application), all of which applications areincorporated herein by reference).

The electron tunneling devices as disclosed in the aforementioned '988,'972, '054, '535 and '935 applications are particularly suited forintegration onto existing chips because combination of metal andinsulating layers forming each electron tunneling device may bedeposited directly on the chips without the need for additionalsemiconductor processing steps. That is, the electron tunneling devicesof the aforementioned applications may be formed monolithically onexisting semiconductor devices without high temperature or crystallinegrowth procedures. Additionally, unlike hybrid integration assemblies,in which separately-fabricated devices are surface mounted or flip-chipbonded onto existing chips, the electron tunneling devices developed bythe assignee of the present invention may be formed directly on thechips themselves. Furthermore, as described in detail in the '988, '972,'054, '535 and '935 applications, the electron tunneling devices asdisclosed in these applications are capable of operating at high speeds,thus enabling these devices to function in optical regimes and at highdata rates. Still further, the electron tunneling devices may beintegrated into the circuitry itself (i.e., formed during thefabrication procedure of the circuitry as a part of the circuitrycomponents), if so desired. Therefore, by incorporating the electrontunneling devices of the aforementioned '988, '972, '054, '535 and '935applications as part of an optical interconnect assembly, a high speedinterconnection solution for use between components on chips, betweenchips and so on may be attained.

Moreover, the electron tunneling devices developed by the assignee ofthe present invention may be fabricated directly adjacent to a waveguideand be configured to cooperate with the waveguide so as to absorb anevanescent field portion of a lightwave traveling through the waveguide.For example, the electron tunneling device may include an antennadesigned to couple light of a particular wavelength (e.g., opticalwavelengths) out of the waveguide and into a tunneling junction regionof the electron tunneling device. Alternatively, the electron tunnelingdevices may be fabricated within a waveguide so as to absorb thepropagating field portion of the a lightwave traveling through thewaveguide. As will be discussed in detail at an appropriate point in thetext below, the concept of combining the electron tunneling devices witha waveguide is significant in that it allows the coupling of lightenergy into and out of the waveguide as well as the directing of lightenergy to electronic devices as electrical energy. This concept may beutilized to provide high speed interconnections between optical andelectronic components, as will be discussed in detail immediatelyhereinafter.

Turning now to the drawings, wherein like components are indicated bylike reference numbers throughout the various figures, attention isimmediately directed to FIG. 1A, which illustrates an approach to theinterconnection of two electron tunneling structures on a chip inaccordance with the present invention. FIG. 1A is a diagrammaticillustration, in perspective view, of an interconnect assembly 10.Interconnect assembly 10 includes a chip 11, which includes circuitry 12formed on top of a substrate 13. A waveguide region 14 is defined onchip 11, and a first electron tunneling device 16 and a second electrontunneling device 18 are formed on top of waveguide region 14. First andsecond electron tunneling devices 16 and 18 may be, for instance, highspeed electron tunneling devices and variants as disclosed in theaforementioned '988, '972, '054, '535 and '935 applications, which highspeed electron tunneling devices are formed of thin film layers ofnon-insulating and insulating materials. Waveguide region 14 may beformed, for example, of polymers, dielectric materials such as glass,fused silica and silicon-on-insulator, photonic crystals, lithiumniobate, organic materials and photonic bandgap materials. In theembodiment illustrated in FIG. 1A, first and second electron tunnelingdevices 16 and 18 include antenna arms 20A-20B and 22A-22B,respectively, defining bowtie antennae. Other antenna designs such as,but not limited to, Vivaldi, Vee, and those designs described in the'935 application, may also be used. First and second electron tunnelingdevices 16 and 18 may be connected to integrated electronic componentsin the existing electronic circuitry (represented by squares 24 and 26)on the chip by, for example, pairs of metal lines 28A and 28B and 30Aand 30B, respectively. The integrated electronic components 24 and 26may be, for example, driver transistors or amplifier transistors.

Still referring to FIG. 1A, a number of different configurations of theinterconnect assembly of the present invention are contemplated. As anexample, first electron tunneling device 16 may be a modulator, asdescribed in the '972 or '054 or '535 application, and second electrontunneling device 18 may be a detector, as described in theaforementioned '988, '972, '054, '535 and '935 applications. In thiscase, an external continuous wave (CW) light source (not shown) may feeda CW light, indicated by an arrow 40, into waveguide 14, then thecircuitry on the chip may cause first electron tunneling device 16(modulator) to modulate the CW light in the waveguide so as to produce amodulated light, indicated by a wavy arrow 42. The manner in which thefirst electron tunneling device may act as a modulator is described indetail in the aforementioned '972 and '054 applications. Waveguideregion 14 may be further configured to act as an interconnect betweenthe first electron tunneling device 16 and second electron tunnelingdevice 18 such that second electron tunneling device 18 (detector)detects modulated light 42 to generate an electrical signal, indicatedby an arrow 44. Electrical signal 44 can then be directed back into theexisting circuitry on the chip or be coupled out to integratedelectronic component 26. Alternatively, second electron tunneling device18 may be configured to detect only a portion of modulated light 42 suchthat a slightly attenuated, output light, indicated by a wavy arrow 46,is further directed through waveguide 14 to be coupled out of the chip.As yet another alternative, second electron tunneling device 18 may bereplaced by a conventional detector which is not based on electrontunneling such as, for example, a semiconductor-based detector.

Continuing to refer to FIG. 1A, interconnect assembly 10 is advantageousin that an optical means of interconnecting various devices on-chip aswell as off-chip is provided without additional complications in thechip circuitry itself. As described in detail in the aforementioned'988, '972 and '056 applications, the electron tunneling devicesdisclosed by the assignee of the present invention may be formed ofreadily depositable materials, such as metals and insulators. As aresult, first electron tunneling device 16 may be formed directly on topof a chip, as shown in FIG. 1A, without interference with the intendedfunction of the integrated electronic components in the chip circuitryor displacing existing circuitry on the chip, using relatively simple,deposition and lithography, rather than semiconductor crystalline growthtechniques. Also, rather than relying upon a direct, hardwire electricalconnection from the portion of the chip circuitry near component 24 tothat near component 26, data may be transferred between the two regionson the chip by the optical interconnection between the first electrontunneling device and the second electron tunneling device. Furthermore,modulated light 46, which contains information as encoded onto firstelectron tunneling device 16 acting as a modulator, may be directed ontoa site away from chip 11 such that the encoded information istransmitted off-chip at optical speeds.

Referring now to FIGS. 1B and 1C, possible configurations for theelectron tunneling devices shown in FIG. 1A are described. FIG. 1Billustrates a cross-sectional view of one embodiment of an electrontunneling device suitable for use in the interconnect assembly of thepresent invention as shown in FIG. 1A. This electron tunneling device issimilar in design to those shown in the aforementioned '988 and '972applications. An electron tunneling device 16B includes a firstnon-insulating layer 50, which forms one of the antenna arms (e.g.,antenna arm 20 in FIG. 1A) of the first electron tunneling device. Inthe embodiment shown in FIG. 1B, first non-insulating layer 50 isdeposited on top of waveguide 14, which in turn has been formed on topof circuitry 12. First non-insulating layer 50 may be, for example, ametal, semi-metal, semiconductor or superconductor. A first layer 52 isdeposited also on top of waveguide 14 such that first layer 52 partiallyoverlaps first non-insulating layer 50. First layer 52 may be, forexample, an amorphous or crystalline insulating material. The portionwhich overlaps with first non-insulating layer 50 may be, for instance,an oxide of the first non-insulating layer or a separately deposited,amorphous insulating layer. A second non-insulating layer 54 isdeposited on top of first layer 52 such that a tunneling junction region60B is formed by the overlapping portions of first non-insulating layer50, first layer 52 and second non-insulating layer 54. Second insulatinglayer 54 defines the other of the antenna arms (e.g., antenna arm 21 inFIG. 1A) of first electron tunneling device 16B, and may be formed of,for example, a metal, semi-metal, semiconductor or superconductor. In atunneling junction region (indicated by a dashed box 60B), first andsecond non-insulating layers are spaced apart from one another such thata voltage (not shown) may be applied thereacross. First layer 52 isfurther configured to cooperate with the materials forming the first andsecond non-insulating layers such that electrons are allowed to traveltherethrough by means of tunneling depending on the voltage placedacross the first and second non-insulating layers. That is, thethickness of first layer 52 as well as the material from which the firstlayer is formed are selected such that first electron tunneling deviceexhibits the desired electron tunneling characteristics. For instance,the first non-insulating layer may be 40 nm of nickel, and the secondnon-insulating material may also be 40 nm of nickel, both deposited bysputtering. The first layer may consist of, for example, a layer ofnickel oxide, 4 nm thick, formed by thermal oxidation.

Referring now to FIG. 1C, a variation of the electron tunneling deviceof FIG. 1B is illustrated. An electron tunneling device 16C is based onthe structures described in the co-assigned '988 application mentionedearlier. Like electron tunneling device 16B shown in FIG. 1B, electrontunneling device 16C includes first and second non-insulating layers 50and 54, respectively, with a first layer 52 disposed therebetween.Additionally, a tunneling region 60C of electron tunneling device 16Cincludes a second layer 62. As described in detail in the '988application, the addition of second layer 62 serves to increase thenonlinearity in the current-voltage characteristics of the electrontunneling device. Moreover, the inclusion of the second layer allows thepossibility of resonant tunneling as the electron transport mechanismthrough the electron tunneling device. Second layer 62 may be, forexample, an amorphous or crystalline insulating layer. For instance, thefirst non-insulating layer may be 40 nm of niobium, and the secondnon-insulating material may be 40 nm of tantalum, both deposited bysputtering. The first layer may consist of amorphous niobium oxide, 1.5nm thick, on top of which is deposited amorphous tantalum oxide, also1.5 nm thick, both deposited by atomic layer deposition.

It should be noted that, the modifications shown in FIGS. 1B and 1C maybe applied to one or both of first and second electron tunneling devices16 and 18 of FIG. 1A. Additional modifications, such as the addition ofthree or more adjacent insulating layers or a combination of metal andinsulating layers between the first and second non-insulating layers asshown in FIGS. 1B and 1C, are also contemplated and discussed in theaforementioned co-assigned U.S. patent applications.

Additional variations on the interconnect assembly of the presentinvention are shown in FIGS. 1D-1F. FIG. 1D is similar to theinterconnect assembly shown in FIG. 1A, but first electron tunnelingdevice 16 has been replaced with an electron tunneling modulator 72.Electron tunneling modulator 72 includes first and second pairs ofantenna arms. First pair of antenna arms 20 and 21 is essentially thesame as that shown in, for example, FIG. 1A, and is designed to receiveinput light 40 and modulate it so as to produce modulated light 42. Asdiscussed in reference to FIGS. 1B and 1C, antenna arms 20 and 21 may beconfigured to overlap such that a tunneling junction region (not shown)is formed. Electrical signals 71A and/or 71B may be provided via wires28A and 28B, respectively, as a modulation signal so as to vary theelectron transport characteristics of the tunneling junction region,thus yielding the modulated light in accordance with the modulationsignal. Electron tunneling device 72 further includes a second pair ofantenna arms 73 and 74, which may be configured to receive an opticalmodulation input 75. Optical modulation input 75 acts as an opticalmodulation signal to vary the electron transport characteristics of thetunneling junction region, thus, again, such that electron tunnelingdevice 72 yields modulated light 42 in accordance with the opticalmodulation signal. Details of such a crossed-bowtie antenna modulatorare disclosed in the aforementioned '972 application. Additionally,second pair of antenna arms 73 and 74 may be connected with anintegrated electronic component 78 in circuitry 12 via wires 76A and76B.

FIG. 1E shows yet another alternative embodiment of an interconnectassembly 80, this time using a surface plasmon device of the '054application as a detector device, in place of second electron tunnelingdevice 18 in interconnect assembly 10 of FIG. 1A. A surface plasmondevice 82 includes a pair of antenna arms 84 and 86, which areconfigured to receive modulated light 42 from first electron tunnelingdevice 16. Antenna arms 84 and 86 direct the modulated light so receivedinto a surface plasmon waveguide region 88 as surface plasmon waves.Surface plasmon waveguide region 88 then provides electrical signal 44in accordance with the received modulated light.

As yet another alternative, an interconnect assembly 90, as shown inFIG. 1F, may include a surface plasmon device 92 acting as an emitter,such as described in the '054 application. For instance, in interconnectassembly 90 as shown in FIG. 1F, surface plasmon device 92 receives anelectrical signal 93 from integrated electrical component 28, which is apart of the chip circuitry. The received electrical signal generatessurface plasmon waves (not shown) in a surface plasmon waveguide region94. A pair of antenna arms 96 and 98 of surface plasmon device 92 actsas an emitter antenna to emit the generated surface plasmon waves as anoutput light 46.

FIGS. 1A-1F illustrate interconnect assemblies in which light couplingfrom the waveguide into and out of electron tunneling devices andsurface plasmon devices is performed using antennae. It should be notedthat other light coupling schemes are also possible. For example, asdisclosed in the '054 application, surface plasmon evanescent couplersand grating couplers may also be used in the interconnect assembly ofthe present invention.

An application of the interconnect assembly of the present invention isshown in FIGS. 2A and 2B. FIG. 2A illustrates a cross-sectional view ofan integrated circuit chip 100A including an optical clock distributionconfiguration. Integrated circuit chip 100A includes circuitry 12disposed on substrate 13 as discussed earlier. Integrated circuit chip100A also includes a tunneling device layer 102 based on an insulator104 with a waveguide layer 110 disposed thereon. Tunneling device layer102 includes two or more electron tunneling devices 116, which areconnected to circuitry 12 through, for example, vias 118. Each one ofthe electron tunneling devices may be configured as a detector asdescribed, for example, in the '988, '972 and '054 applications. In theintegrated circuit chip shown in FIG. 2A, an optical signal 120,carrying a clock signal shown as a waveform 122, is edge-coupled intowaveguide layer 110. Optical signal 120 may have a sufficiently longwavelength (e.g., 1550 nm) such that the optical signal is not absorbedby, for example, a silicon substrate or silicon components in thecircuitry but only by the electron tunneling devices. As optical signal120 is guided through waveguide layer 110, each one of electrontunneling devices 116 detects a portion of the optical signal, convertsthe optical signal into an electrical signal (not shown) andcommunicates the electrical signal to circuitry 12. In this way, theclock signal encoded onto optical signal 120 is very quickly distributedacross the entire chip with minimal clock phase skew.

A variation of the optical distribution configuration of FIG. 2A isillustrated in FIG. 2B, showing a cross-sectional view of an integratedcircuit chip 100B. Like integrated circuit chip 100A of FIG. 2A,integrated circuit chip 100B includes substrate 13 and waveguide 110,but the electronic circuitry and electron tunneling device layers havebeen combined. A combination layer 130 includes circuitry 132 withelectron tunneling devices 116 monolithically integrated thereon suchthat electron tunneling devices 116B are disposed alongside electricalcomponents (not individually shown) in the circuitry layer. Electrontunneling devices 116B may be formed during the same fabrication stepsas those used to form circuitry 132 or may be formed separatelyfollowing the fabrication of circuitry 132.

The optical clock distribution configurations shown in FIGS. 2A and 2Bpresent an improvement over the conventional, electrical clockdistribution schemes, in which clock signals are provided as electricalsignal through electrical lines that take up chip real estate, producesignificant clock skew and produce electromagnetic pickup. The opticalclock distribution configurations of FIGS. 2A and 2B avoid theseproblems inherent to electrical clock signals by taking advantage of thefact that the interconnect assembly of the present invention, includingthe electron tunneling devices and waveguide, may be added on top of anexisting integrated circuitry chip. It is often a difficult task in chiplayout design to ensure that the clock signal reaches all parts of thechip simultaneously without degradation and while maintaining a constantphase across the chip. Since optical signals in waveguides travel muchmore quickly and more directly than electrical signals in electricallines, an optical clock signal may be distributed over the chip muchmore quickly than an electrical clock signal. The optical clock signalbroadcast into the waveguide layer may be picked up by the electrontunneling devices through, for instance, vias where needed.

Various modifications to the optical clock distribution configuration ofFIGS. 2A and 2B are contemplated. One such example is shown in FIGS. 3Aand 3B. Like previously discussed embodiments of the present invention,an integrated circuit chip 150 shown in FIG. 3A includes circuitry 12 ontop of a substrate 13. Like integrated circuit chip 100A of FIG. 2A,integrated circuit chip 150 also includes tunneling device layer 102.Integrated circuit chip 150 further includes a modified waveguide layer152, which is designed to receive optical signal 120 carrying a clocksignal 122 when the optical signal is incident normally on modifiedwaveguide layer 152. A grating coupler 154, which is integrated intomodified waveguide layer 152, couples optical signal 120 into modifiedwaveguide layer 152 such that optical signal 120 is radially broadcastthroughout modified waveguide layer 152 as an optical clock signal(represented by arrows 156).

Details of modified waveguide layer 152 as well as tunneling devicelayer 102 are more readily apparent in FIG. 3B, which illustratesintegrated circuit chip 150 in cross section. As shown in FIG. 3B,modified waveguide layer 152 includes grating coupler 154, which isdesigned to receive optical signal 120 and to direct the optical signalso received throughout modified waveguide layer 152 as optical clocksignal 156. Optical clock signal 156 is picked up by electron tunnelingdevices 116 at desired points across the integrated circuit chip.Electron tunneling devices 116 then communicate the optical clock signalto electrical components in the circuitry wherever needed.

As in the case of integrated circuit chip 100A of FIG. 2A, the opticalclock distribution scheme used in integrated circuit chip 150 isadvantageous because the optical clock signal is distributed over theentire chip within picoseconds without being hampered by electricaldelays. As a result, the clock signal received at the chip circuitrydoes not experience significant delay that may cause phase differencesin different part of the chip. Also, since the optical clock signal istransmitted optically and is converted to an electrical signal by anelectron tunneling device only where needed, electromagnetic pickup isreduced in comparison to conventional, electrical clock distributionthrough electrical transmission lines.

Various modifications to the optical clock distribution schemes shown inFIGS. 2A-2B and 3A-3B are possible. For example, the optical clocksignal may be broadcast over the integrated circuit chip throughfree-space and subsequently picked up by the electron tunneling devicesat various locations on the integrated circuit chip. Such a free-spacetransmission scheme may include, for instance, additional opticalcomponents such as lenses, holographic optical elements and filters.Other modifications may be apparent to those skilled in the art whileremaining within the spirit of the present invention.

Turning now to FIGS. 4A and 4B, still other alternative embodiments ofan interconnect assembly of the present invention using optical fibersare illustrated. FIG. 4A shows an interconnect assembly 200.Interconnect assembly 200 includes first and second chips 202 and 204,respectively. First chip 202 includes a substrate 206, on whichcircuitry 208 is formed. Similarly, second chip 204 includes a substrate210 with circuitry 212 formed thereon. The first and second chipsfurther include a first electron tunneling device 216 and a secondelectron tunneling device 218, respectively, formed thereon. In theembodiment as shown in FIG. 4A, first electron tunneling device 216 isconfigured to act as an emitter, such as those disclosed in the patentapplications referenced above. First electron tunneling device 216 emitsa light beam 220, which is focused by a first lens arrangement 222 ontoan optical fiber input 224. Light beam 220 is then transmitted throughan optical fiber 226 in the direction indicated by an arrow 228 towardan optical fiber output 230. At optical fiber output 230, light beam 220is then focused by a second lens arrangement 232 onto second electrontunneling device 218. For instance, second electron tunneling device 218may be an electron tunneling device, as disclosed in the '988, '972,'054, '535 and '935 applications, which is configured to act as adetector so as to receive light beam 220. Alternatively, a conventionaldetector, such as a silicon-based detector, may be used as secondelectron tunneling device 218. In this way, an optical interconnectionis established between devices on first and second chips 202 and 204,thereby allowing transfer of data therebetween. Such an opticalinterconnection is advantageous over, for example, electricalinterconnections in terms of speed, signal loss, propagation distanceand drive power.

FIG. 4B shows an alternative embodiment of an interconnect assemblyusing optical fiber. An interconnect assembly 250 is similar tointerconnect assembly 200 of FIG. 4A with a number of key differences.Interconnect assembly 250 includes a laser 252 configured to direct aninput laser light (not shown) through an input optical fiber 254 in thedirection indicated by an arrow 256. Input optical fiber 254 directs theinput laser light into an optical circulator 258, which then directs theinput laser light through a fiber segment 260 toward first electrontunneling device 216. In the embodiment shown in FIG. 4B, first electrontunneling device 216 is configured to act as a reflective modulator,which receives and modulates the input laser light. As a result, a lightbeam 262 as shown in FIG. 4B includes both the input laser light and amodulated light (not shown) as reflected from first electron tunnelingdevice 216 such that fiber segment 260 contains light traveling into andout of circulator 258, as indicated by a double-headed arrow 263.Circulator 258 is configured such that any light entering the circulatorfrom input optical fiber 254 is directed into fiber segment 260 whilelight entering the circulator from fiber segment 260 is directed towardoptical fiber 226 in direction 228. In this way, modulated light fromfirst electron tunneling device 216 is directed through optical fiber226 and detected at second electron tunneling device 218. It is notedthat multi-mode optical circulators are not commercially available atthe current state of technology. Therefore, input optical fiber 254 andfiber segment 260 shown in FIG. 4B would be required to be single modefibers if single mode circulators are used. However, it is anticipatedthat future development of a multi-mode optical circulator would enablethe interconnect scheme of FIG. 4B to be compatible with multi-modeoptical signal transmission, therefore the use of single mode opticalfiber as well as the use of multi-mode optical fiber in theconfiguration shown in FIG. 4B are considered to be within the spirit ofthe present invention. Alternatively, the optical circulator may bereplaced by an optical coupler, albeit with loss of optical power intofiber 226.

Still referring to FIG. 4B, first electron tunneling device 216 may beconfigured to receive a modulation signal from on-chip circuitry 208.Consequently, data from circuitry 208 may be encoded onto the modulatedlight produced at first electron tunneling device 216 and opticallytransmitted at high speeds to devices on chip 204 by way of secondelectron tunneling device 218. Also, second electron tunneling device218 may be configured with a second optical circulator such that lightreflected by second electron tunneling device 218 may be passed down achain or around a token ring.

Alternative optical interconnect configurations using optical fiber areshown in FIGS. 4C and 4D. As shown in FIG. 4C, an interconnect assembly270 includes first and second chips 202 and 204, respectively. Inaddition, interconnect assembly 270 includes first and second waveguides272 and 274, which are connected with first and second electrontunneling devices 216 and 218, respectively. First and second waveguides272 and 274 couple light into or out of the electron tunneling devicessuch that light from the electron tunneling devices may be fed intooptical fiber 226 and vice versa. For instance, if first electrontunneling device 216 is configured as an emitter (as described, forexample, in the '972 or the '054 application), light emitted by firstelectron tunneling device 216 is coupled through first waveguide 272 andinto one end of optical fiber 226. The light then travels throughoptical fiber 226 and, at an opposing end of the optical fiber, iscoupled through second waveguide 274 and into second electron tunnelingdevice 218, which receives the transmitted light. Optical fiber 226 maybe, for example, butt-coupled to first and second waveguides 272 and274, which are disposed on top of circuitry 208 and 212, respectively,as shown in FIG. 4C. Instead, the waveguides may be embedded in the chipcircuitry, as shown in FIG. 4D as first and second waveguides 282 and284. Additionally, alignment aids, such as first and second v-grooves286 and 288, may be included in the chips to assist in the alignment ofthe optical fiber with respect to the waveguides.

Yet another alternative embodiment of an interconnect assembly is shownin FIG. 5. FIG. 5 illustrates an interconnect assembly 300 in a freespace optical interconnect scheme. Interconnect assembly 300 includes afirst chip 310, which includes a first substrate 312 and first circuitry314. A first plurality of electron tunneling devices 316 a-316 e aredisposed on first circuitry 314. Interconnect assembly 300 also includesa complementary, second chip 320, which includes a second substrate 322,second circuitry 324 and a second plurality of electron tunnelingdevices 326 a-326 e formed thereon. In the embodiment shown in FIG. 5,first chip 310 and second chip 320 are positioned such that firstplurality of electron tunneling devices 316 a-316 e on chip 310 arespaced apart from and in opposing relationship with second plurality ofelectron tunneling devices 326 a-326 e on chip 322. For instance, firstplurality of electron tunneling devices 316 a-e are configured to eachemit a light beam of at least a given frequency, indicated by arrows 328and second plurality of electron tunneling devices 326 a-326 e areconfigured to detect light of at least the given frequency. Interconnectassembly 300 further includes a lens arrangement 330, which isconfigured to direct light from each of first plurality of electrontunneling devices 316 a-316 e to a corresponding one of second pluralityof electron tunneling devices 326 a-326 e. For instance, as shown inFIG. 5, lens 330 is designed such that light beam 328 emitted byelectron tunneling device 316 b on chip 310 is directed to electrontunneling device 326 b on chip 320. Moreover, one or more additionaloptical components, as represented by a component 332, may also beincluded to perform additional optical operations. For example,component 332 may be another lens, filter, holographic optical element,reflector, grating, transmissive spatial light modulator, etc. In thisway, data may be transferred optically from chip 310 to chip 320 througha free space optical interconnect scheme.

Various modifications to the free space, interconnect assembly of FIG.5. Optical components, such as mirrors and beamsplitters, may be addedto enable a non-parallel configuration of the chips. Also, lensarrangement 330 may be configured to cooperate with the electrontunneling devices on chips 310 and 320 such that operation of theinterconnect assembly in the reverse direction is possible. That is, itis possible to configure the second plurality of electron tunnelingdevices on chip 320 to act as emitters and configure the first pluralityof electron tunneling devices on chip 310 to act as detectors so as toenable the transfer of data from chip 320 to chip 310. Also, component332 may be configured as, for instance, a waveguide including a gratingor evanescent coupler such that at least portions of light beams 328 and328′ may be transferred out of interconnect assembly 300. In this case,an additional light beam (not shown) may also be inserted into theinterconnect assembly at component 332 configured as a waveguide.Furthermore, the free space interconnect assembly of FIG. 5 may becombined, for instance, with the optical clock distribution schemesillustrated in FIGS. 2, 3A and 3B such that, rather than having anoptical clock signal be indiscriminately broadcast over the entire chip,the optical clock signal may be selectively imaged onto specificelectron tunneling devices on the chip.

As described above, the interconnect assembly of the present invention,including electron tunneling devices, is advantageous due to the highspeed and integrability with silicon devices (such as chips). Theinterconnect assembly of the present invention allows high speedinterconnection between components on a chip, between chips, betweenboards and racks, etc., by taking advantage of high speeds possible inthe optical regime. It should be noted that an important benefit of theapproach of the present invention involving the use of electrontunneling devices in optical interconnect arrangements is the fact thatthe present invention takes advantage of the ability of the electrontunneling devices to detect, modulate or emit light directly into or outof a waveguide or optical fiber. That is, the electron tunneling devicetechnology developed by the assignee of the present invention allowsefficient coupling and conversion between optical and electrical signalsin a compact configuration which is compatible with existing integratedcircuit chip technology. This feature is in contrast to conventionalsilicon devices with waveguides, in which light traveling through thewaveguide must be redirected away from the waveguide and into thesilicon in order to be detected or otherwise acted upon.

It is notable that the electron tunneling devices, for example as shownin FIGS. 1A-1F, 2A-2B and 3A-3B, may be fabricated directly adjacent toa waveguide to allow fast, guided transmission of optical signals fromone electron tunneling device to another. Furthermore, the electrontunneling devices may be used to couple light energy into and out of thewaveguide as well as to direct light energy to electronic devices aselectrical energy. Further details of such waveguide-coupled assembliesare discussed in further detail immediately hereinafter.

Turning now to FIGS. 6A and 6B, a waveguide-coupled assembly 400fabricated in accordance with the present invention is illustrated.Waveguide-coupled assembly 400 includes a substrate 402, which supportsa first insulating layer 404. For example, substrate 402 may be formedof silicon, while insulating layer 404 is formed of silicon dioxide.Waveguide-coupled assembly 400 further includes an optical waveguidelayer 406 and a second insulating layer 408. Optical waveguide layer 406and second insulating layer 408 cooperate to define a raised, ribwaveguide section 410. Rib waveguide section 410 includes an opticalinput end 412, which directs input light incident thereon (indicated byan arrow 414) into the rib waveguide section. Waveguide-coupled assembly400 further includes at least one electron tunneling device 416, whichis formed on top of rib waveguide section 410. Electron tunneling device416 is designed to receive a portion of input light 414, modulate thereceived portion of the input light, and produce a modulated, outputlight (indicated by an arrow 418), which output light 418 is directedtoward an optical output end 420. For instance, bowtie antenna arms 422and 424 of electron tunneling device 416 may be formed in a particularshape and size so as to pick up a portion of the input light of a givenwavelength. Different antenna designs may also be used to optimizecoupling to particular waveguide modes, such as transverse-magnetic andtransverse-electric modes. Alternatively, other coupling arrangements,such as grating couplers, may be used in place of an antenna in electrontunneling device 416. Also, a coupling arrangement and an electrontunneling component may be formed at physically separate locations whilestill being connected with each other such that an optical or electricalsignal may be communicated therebetween. Electron tunneling device 416may be a modulator fabricated in accordance with the disclosure in theaforementioned '988, '972, '054, '535 and '935 applications. As apossible variation, waveguide-coupled assembly 400 of FIG. 6A is shownto include a linear array of four electron tunneling devices 416 toprovide additional interaction with an evanescent light field portion ofthe input light so as to provide output light 418 having a desireddegree of modulation. More or fewer electron tunneling devices may beused in a linear or two-dimensional array such that the resultingwaveguide-coupled assembly provides a particular function. That is, byusing more than one electron tunneling devices in the waveguide-coupledassembly, the interaction length between the input light and theelectron tunneling devices may be effectively increased. Couplingbetween the antenna and waveguide may also be controlled by varying thespacing or cladding thickness between antenna and waveguide core. Anycombination of the aforedescribed variations is also considered to bewithin the scope of the present invention.

It should be noted that, although waveguide-coupled assembly 400 of FIG.6A is shown to include a silicon-on-insulator rib waveguide, otherwaveguide types, such as buried waveguides, fully etched waveguides, orphotonic crystal waveguides, and different waveguide materials, such asglass or polymer, may also be used. In many instances, higher index andthinner waveguides couple more efficiently to the antenna and also takeup less space on chip.

An example of the interaction of the electron tunneling devices with theinput light is discussed in reference to FIG. 6B, showing across-sectional view of waveguide-coupled assembly 400 of FIG. 6A. Asshown in FIG. 6B, electron tunneling devices 416 a-416 d pick upevanescent field portions of input light 414 (shown as arrows 430 a-430d), modulate the received portions, then re-transmit modulated light(indicated by arrows 432 a-432 d) back into waveguide layer 406 so as toprovide modulated, output light 418. Evanescent coupling between the ribwaveguide region and the electron tunneling devices is particularlyefficient for thin, high index waveguides.³

Continuing to refer to FIGS. 6A and 6B, it is noted that furthermodifications to waveguide-coupled assembly 400 are possible. Forexample, each of electron tunneling devices 416 a-416 d may beconfigured to pick up a different wavelength of input light such thatwaveguide-coupled assembly 400 acts as a wavelength-dependent modulatorof input light, which input light may include a variety of wavelengths.Alternatively, one or more of electron tunneling devices 416 a-416 d maybe configured as a detector (see, for example, aforementioned '988, '972and '054 applications) so as to receive a portion of the input light andgenerate an electrical signal in accordance with the input light soreceived, which electrical signal may be directed to an electronicdevice located off of substrate 402 or also supported on the substrate.As yet another alternative, one or more of electron tunneling devices416 a-416 d may be configured as an amplifier (see, for instance,aforementioned '972 and '054 applications) so as to receive a portion ofthe input light or a portion of modulated light, as produced by anotherof the electron tunneling devices, and produce an amplified outputlight. In still another alternative, one or more of the electrontunneling devices may be configured as an emitter (see, for example,aforementioned '972 and '054 applications) so as to emit additionallight into the rib waveguide region to contribute to the output light.Still further, one or more of the electron tunneling devices may beconfigured to re-emit the portion of input light received at thatelectron tunneling device, for example, in a direction away from thewaveguide and the substrate so as to produce a free-space optical signalin accordance with the input light. As yet another option, one or moreof the electron tunneling devices may be configured to receivefree-space illumination and re-transmit the received optical energy intothe waveguide.

FIGS. 6C and 6D illustrate still more alternative configurations towaveguide-coupled assembly 400 shown in FIGS. 6A and 6B. For example, asshown in FIG. 6C, modified electron tunneling devices 416 a′-416 d′ areintegrated into a modified insulating layer 404′, rather than beingformed on top of rib waveguide section 410. As in the embodimentillustrated in FIGS. 6A and 6B, the modified electron tunneling devicesalso couple to evanescent field portions of input light 414 (shown asarrows 430 a′-430 d′), modulate the received portions, then re-transmitmodulated light (indicated by arrows 432 a′-432 d′) back into waveguidelayer 406 so as to provide modulated, output light 418. In contrast,modified electron tunneling devices 416 a″-416 d″, shown in FIG. 6D, areintegrated into a modified optical waveguide layer 406″. In this case,input light 414 directly couples into modified electron tunneling device416 a″, which re-emits a modulated light 432 a″. Modulated light 432 a″then couples into modified electron tunneling device 416 b″, and so onuntil the output from the last device in the series, in this casemodified electron tunneling device 416 d″, becomes output light 418.Thus, each one of the configurations shown in FIGS. 6B-6D isadvantageous in different situations, depending on the level ofintegration required. For example, although the electron tunnelingdevices are most readily fabricated on top of the rib waveguide region,it may be desirable in certain cases to have the direct coupling of theprincipal portion of the input light with the electron tunneling devicesas allowed by the configuration shown in FIG. 6D. Alternatively, closercoupling of the evanescent field portions of input light 414 may beenabled by the positioning of the electron tunneling regions as shown inFIG. 6C without drastically altering the lightwave-guidingcharacteristics of the rib waveguide region.

Attention is now directed to FIG. 6E, which illustrates an end-firevariation of the waveguide-coupled assembly of FIG. 6A, generallyindicated by a reference number 450. To the extent thatwaveguide-coupled assembly 450 resembles previously describedwaveguide-coupled assembly 400, for example, with respect to its layeredstructure and the location of the electron tunneling devices, suchdescriptions are not repeated for purposes of brevity. A substrate 451of waveguide-coupled assembly 450 includes first and second v-grooves452 and 453, respectively, for accommodating an input optical fiber 454and an output optical fiber 456, respectively. For example, inputoptical fiber 454 includes a fiber core 458 surrounded by a cladding460, and is designed to direct an input optical signal 462 therethroughand into rib waveguide region 410 as input light 414. Output light 418provided at optical output end 420 is then coupled into output opticalfiber 456. As shown in FIG. 6E, output optical fiber 456 includes afiber core 464 surrounded by a cladding 466 so as to direct at least aportion (indicated by an arrow 468) of output light 418 away fromoptical output end 420. The coupling of optical fiber to the ribwaveguide region enables ready insertion of waveguide-coupled assembly450 into optical fiber-based systems, such as long distancecommunication systems. This end-fire embodiment allows higher couplingefficiency for single-mode fibers. Furthermore, inclusion of alignmentaids, such as v-grooves 452 and 453 in substrate 451 allowsself-alignment of optical fiber with the waveguide-coupled assembly ofthe present invention.

Referring now to FIGS. 7A-7D, still further variations of thewaveguide-coupled assembly of the present invention are discussed. FIG.7A shows a waveguide-coupled assembly 500, which includes a shapedwaveguide 502. Shaped waveguide 502 includes first and second taperedsections 504 and 506, respectively, on either side of a middle section507. First and second chirped, focusing grating couplers (surrounded bydashed lines 508 and 510, respectively) are formed near opposite ends ofshaped waveguide 502 such that first chirped, focusing grating coupler508 receives an input optical signal 512 and couples the optical signalso received into shaped waveguide 502 as an input light (indicated by anarrow 514). Input light 514 is then directed through first taperedsection 504 into middle section 507. One or more electron tunnelingdevices (three are shown, indicated by reference numerals 516 a-516 c)are disposed on top of middle section 507 and are configured for, forexample, modulating the input light then producing a modulated, outputlight (indicated by an arrow 518). Modulated, output light 518 is thendirected through second tapered section 506 and coupled out of shapedwaveguide 502 through second chirped, focusing grating coupler 510 as anoutput optical signal 520.

FIG. 7B is an illustration of an integrated optical transceiver chipincluding the waveguide-coupled assembly of FIG. 7A. The integratedoptical transceiver chip, generally indicated by reference numeral 550,includes a substrate 552 on which various components are supported, aswill be described in detail immediately hereinafter. Substrate 552includes an etched-out section 554, in which a modifiedwaveguide-coupled assembly 500′, which is similar in design towaveguide-coupled assembly 500 as shown in FIG. 7A. To the extent thatwaveguide-coupled assembly 500′ resembles previously describedwaveguide-coupled assembly 500, for example, with respect to its taperedwaveguide structure, focused grating couplers and the location of theelectron tunneling devices, such descriptions are not repeated forpurposes of brevity. An array of electron tunneling devices 516′ ofwaveguide-coupled assembly 500′ are connected with modulation inputs 556a and 556 b, which lead from circuitry 558 supported on substrate 552.Circuitry 558 is also connected with a detector 560, which is alsosupported on substrate 552, via leads 562 a and 562 b. Power may besupplied to circuitry 558 through DC power lines 564 a and 564 b.

Referring now to FIG. 7B in conjunction with FIG. 7C, one example of theoperation of integrated optical transceiver chip 550 is described inreference to a schematic 580 as shown in FIG. 7C. It is noted thatcorresponding components in the two figures are labeled with the samereference numbers for clarity. In one possible configuration, detector560 may be designed to receive an optical signal 582, including dataencoded thereon, and to provide an electrical, detector signal (notshown), also including the data, via leads 562 a and 562 b to circuitry558. Circuitry 558 may include, for example, electrical components suchas bias control/automatic gain control (AGC) 584, a pre-amplifier 586, aclock recovery circuit 588 as well as a modulator driver 590. Modulatordriver 590 generates a modulation signal in accordance with the detectorsignal and directs the modulation to the array of electron tunnelingdevices of waveguide-coupled assembly 500′. As a result, when acontinuous wave (CW) light input 592 is incident on first chirped,focusing grating coupler 508′, the array of electron tunneling devicesmodulate the CW light input and, consequently, waveguide-coupledassembly 500′ provides a modulated light output 594.

FIG. 7D illustrates a further variation on the waveguide-coupledassembly of the present invention as illustrated in FIG. 7A. FIG. 7D isa diagrammatic view, in cross section, of a modified waveguide-coupledassembly 600. Modified waveguide-coupled assembly 600 includeswaveguide-coupled assembly 500, as shown in FIG. 7A, supported on asubstrate 602 with an insulating layer 604 disposed therebetween. Inputlight 512 is provided through an input optical fiber 610, which includesa fiber core 612 surrounded by a cladding 614. As described previouslyin reference to FIG. 7A, waveguide-coupled assembly 500 provides amodulated, output light 520. In the case of modified waveguide-coupledassembly 600, output light 520 is received by an output optical fiber620, which also includes a fiber core 622 surrounded by a cladding 624for guiding the output light away from the modified waveguide-coupledassembly.

Turning now to FIGS. 8A-8C, several packaging options for integratedoptical transceiver chip 550 as shown in FIG. 7B are described. FIG. 8Ashows a parallel optical transceiver 650 including a transceiver module652 containing a plurality of integrated optical transceiver chips 550therein (not visible). A single mode fiber 654 serves as a CW input formodulation. A plurality of pin-outs (indicated by dashed bracket 656)serves to provide the various RF inputs/outputs as well as DC powerinput. Transceiver module 652 includes an input receptacle 658 a and anoutput receptacle 658 b, both of which are designed to accept multi-modefiber (MMF) ribbons. For example, a first MMF ribbon 660 a may provide aplurality of optical data inputs for the plurality of integrated opticaltransceiver chips, while a second MMF ribbon 660 b may serve to extractthe plurality of optical data outputs produced by the integrated opticaltransceiver chips.

FIG. 8B illustrates a scheme in which two or more chips may be opticallyinterconnected. A chip-to-chip optical backplane 700 is designed toaccept a lead frame-mounted chip 702. Lead frame-mounted chip 702includes a die 704 containing circuitry and connected to a lead frame706 including a plurality of pin-outs (indicated by a dashed bracket708). Optical backplane 700 includes an integrated circuit socket 710including a plurality of receptacles (indicated by a dashed bracket 712)corresponding to the pin-outs of the lead frame-mounted chip. Opticalbackplane 700 further includes a MMF ribbon input 714, a MMF ribbonoutput 716, CW input 718 and DC power input through leads 720 a and 720b. Integrated circuit socket 710 includes a plurality of theaforedescribed optical transceiver chips so as to directly connect achip in a standard lead frame package with the optical transceivers.

FIG. 8C illustrates yet another packaging option for the opticaltransceiver chip of the present invention. An optical processor chip 750includes a package 752 containing a plurality of optical transceiverchips (not visible). Package 752 includes an optical window 754, whichallows direct, optical connection of the optical processor chip withother optical components through a parallel optical bus (indicated byarrows bracketed by a dashed bracket 756). Package 752 also includes theusual inputs for CW optical input (an optical fiber 758) and DC powerinput (leads 760 a and 760 b).

Although each of the aforedescribed embodiments have been illustratedwith various components having particular respective orientations, itshould be understood that the present invention may take on a variety ofspecific configurations with the various components being located in awide variety of positions and mutual orientations and still remainwithin the spirit and scope of the present invention. Furthermore,suitable equivalents may be used in place of or in addition to thevarious components, the function and use of such substitute oradditional components being held to be familiar to those skilled in theart and are therefore regarded as falling within the scope of thepresent invention. For example, a reflective layer may be disposedbetween the circuitry layer and the waveguide layer for better isolationof the waveguide layer from the circuitry as well as for improvedcoupling of optical signals from the waveguide into the electrontunneling devices (see, for example, the '935 application). Also, thewaveguide layer shown, for example, in FIG. 1A may be a separatelydeposited waveguide or a silicon-on-insulator (SOI) integratedwaveguide. Furthermore, the substrate itself may be opticallytransmissive or guiding such that the optical signal may be providedfrom the substrate side of the interconnect arrangement rather thanbeing edge-fed or incident from the top side. Still further, a varietyof light coupling arrangements may be included in the embodiments of thepresent invention such as, and not limited to, antennas (as shown in,for instance, FIGS. 1A and 6A), grating couplers and surface plasmonevanescent couplers, all of which are discussed in detail in theaforementioned '988, '972, '054, '535 and '935 applications.

Therefore, the present examples are to be considered as illustrative andnot restrictive, and the invention is not to be limited to the detailsgiven herein but may be modified within the scope of the appendedclaims.

REFERENCES

1. Neil Savage, “Linking with Light,” IEEE Spectrum, vol. 39, Issue 8,pp. 32-36 (2002).

2. A. F. J. Levi, “Optical Interconnects in Systems,” Proceedings of theIEEE, vol. 88, pp. 750-757 (2002).

3. Brian J. Soller and Dennis G. Hall, “Energy transfer at opticalfrequencies to silicon-based waveguiding structures,” J. Opt. Soc. Am.A, vol. 18, no. 10, pp. 2577-2584 (2001).

1. An optoelectronic device, comprising: a formation of integratedlayers, said integrated layers being configured so as to define at leastone integrated electronic component; and an electron tunneling devicethat is configured for electrical communication with said integratedelectrical component, said electron tunneling device including first andsecond non-insulating layers in a spaced apart, confronting relationshipwith one another so that a voltage difference can be supportedtherebetween, an arrangement supported between the first and secondnon-insulating layers including at least one layer for producingelectron tunneling between and to said first and second non-insulatinglayers, and an antenna structure that is formed in electricalcommunication with said first and second non-insulating layers as partof said tunneling device for providing an external communication withthe electron tunneling device.
 2. The device of claim 1 wherein saidantenna is further configured to perform said external communicationusing an optical radiation.
 3. The device of claim 2 including anoptical waveguide for carrying said optical radiation and said antennais in optical communication with said optical waveguide.
 4. The deviceof claim 3 wherein said optical waveguide carries a clock signal for useby said integrated electronic component.
 5. The device of claim 4wherein said optical waveguide is configured for receiving said clocksignal from an external source as part of an overall broadcast of theclock signal.
 6. The device of claim 2 wherein said antenna receivessaid optical radiation from an external source and said tunneling deviceis configured for interacting with the integrated electronic componentresponsive to said optical radiation, based on said electricalcommunication.
 7. The device of claim 6 wherein said optical radiationincludes a clock signal and said tunneling device is configured forcommunicating the clock signal to the integrated electronic component.8. The device of claim 6 wherein said optical radiation is emanated froman optical fiber and said antenna is configured for receiving theoptical radiation from the optical fiber.
 9. The device of claim 2wherein said integrated electronic component is configured fortransferring an electrical signal to said tunneling device, as saidelectrical communication, and said tunneling device, in turn, generatessaid optical radiation from said antenna that is responsive to theelectrical signal.
 10. The device of claim 9 wherein said antenna isconfigured to couple said optical radiation into an optical fiber. 11.The device of claim 1 wherein said integrated electronic component isconfigured for supplying a bias voltage to said electron tunnelingdevice as said voltage difference between the first and secondnon-insulating layers.
 12. An arrangement, comprising: a plurality ofthe optoelectronic devices of claim 1 in a spaced apart relationshipwith one another and configured for communication therebetween using theantenna structure of each optoelectronic device wherein the formation ofintegrated layers of all of the optoelectronic devices cooperate todefine a single integrated circuit chip.
 13. An arrangement, comprising:a plurality of the optoelectronic devices of claim 1 configured forcommunication therebetween using the antenna structure of eachoptoelectronic device wherein the formation of integrated layers foreach one of the optoelectronic devices is defined by one of a pluralityof individual integrated circuit chips.
 14. An optoelectronic device,comprising: a formation of integrated layers, said integrated layersbeing configured so as to define at least one integrated electroniccomponent; and an electron tunneling device that is (i) supporteddirectly by at least a portion of the formation of integrated layers,(ii) configured for an electrical communication with said integratedelectrical component to provide an interaction therewith, and (iii)configured for an external optical communication in cooperation withsaid interaction.